State-of-the-art complex programmable logic devices (CPLDs) typically incorporate a basic sum-of-products architecture where two or more product terms are followed by a sum term to support different combinatorial (e.g., Boolean) functions. An AND gate generates the combinatorial product of its inputs, while an OR gate generates the combinatorial sum of its inputs. A product term (PT) is a configuration of AND gates that combine to generate a single combinatorial product of the inputs to that AND gate configuration. Similarly, a sum term (ST) is a configuration of OR gates that combine to generate a single combinatorial sum of the inputs to that OR gate configuration. The basic sum of products structure of multiple product terms feeding a single sum term, commonly referred to as a generic logic block (GLB), is typically repeated multiple times within a CPLD, with each GLB programmably interconnected via routing resources with other GLBs and with the CPLD inputs and outputs. A Boolean product/sum term of N inputs typically requires on the order of 2N AND/OR gates to implement. For a given CPLD, a limited number of gates are available to implement GLBs.
One metric of recent importance in programmable logic devices is the PT width, i.e., the total number of inputs that are available to a given product term within the device to generate a single PT output.
Another important metric for programmable logic devices is the ST width, i.e., the total number of product terms that are available to a given sum term within the device to generate a single sum-of-products output.
The trend toward wider address and data/control busses in recent microprocessor designs has led to the desire for CPLDs that can implement wide PTs. Since wide PTs are more expensive in gate count than narrow PTs, these devices typically implement this capability at the cost of the total number of PTs available.
Various approaches to this problem have been used, with limited success. One such approach involves supporting the cascading of narrow GLBs, i.e., GLBs that support narrow-width PTs. In this approach, some of the inputs of a wide Boolean function maybe fed to a narrow GLB where a first PT output is formed. This PT output is then input to another narrow GLB. This second GLB also receives the remaining inputs of the function, thereby forming the equivalent of a single, wide GLB. Disadvantages of this approach include the delays that result from routing signals from the output of the first narrow GLB to the input of the second narrow GLB and the delays associated with passing some signals sequentially through multiple narrow GLBs. Other approaches such as adding levels of OR functions on the output, inverting PT outputs before feeding them to the OR array to increase the effective number of single-bit PTs, and using XOR functions in the output cells have also provided some additional flexibility, with corresponding trade-offs.